SAR with Digital Beamforming
Why digital beamforming?
ADD MATERIAL FROM THESIS
Why digital beamforming?
ADD MATERIAL FROM THESIS
This section presents a case study consisting of a 32-element digital phased array radar. The raw data is processed onboard the satellite to reduce the amount of data downloaded to ground.
The FMC standard defines 10 SERDES, supporting FMC cards with 4 ADCs and 4 DACs with serial data interfaces, capable of synthesizing and sampling the baseband signals for 4 radiating elements of the antenna. Each SpaceVPX DSP acts on the amplitude and the phase at the 4 signals sent to and received from each radiating element to steer the beam in the desired angle.
The flexibility of the CPU is key to implement the star topology selected for this application. The CPU must be able to split the redundant FPs (4 lanes each) as 8 independent UTPs (1 lane). This way the data from the ADCs is preprocessed in the DSP and sent to the CPU for data formatting adding time stamps, channel identifier, redundancy information, etc. The Formatter implemented in a SpaceVPX CPU reroutes the data to the corresponding DSP to perform the next step in the processing chain. In addition to formatting data, the CPU implements the functionality of the SpaceVPX System Controller.
The local memory on the DSP board buffers the data transferred between the FMC and the SpaceVPX interface. If the duty cycle of the conversion windows used to sample the echo signal and the sampling frequency are high, then the serial data interface between each DSP module and the CPU module will not support the data rate generated by the four ADCs on the FMC card. In that case, the unused serial data interfaces available on each DSP module can be used to connect the DSP modules to each other, resulting in a mesh topology with a distributed Data Switch.
The FMC standard defines 10 SERDES, supporting FMC cards with 4 ADCs and 4 DACs with serial data interfaces, capable of synthesizing and sampling the baseband signals for 4 radiating elements of the antenna. Each SpaceVPX DSP acts on the amplitude and the phase at the 4 signals sent to and received from each radiating element to steer the beam in the desired angle.
The flexibility of the CPU is key to implement the star topology selected for this application. The CPU must be able to split the redundant FPs (4 lanes each) as 8 independent UTPs (1 lane). This way the data from the ADCs is preprocessed in the DSP and sent to the CPU for data formatting adding time stamps, channel identifier, redundancy information, etc. The Formatter implemented in a SpaceVPX CPU reroutes the data to the corresponding DSP to perform the next step in the processing chain. In addition to formatting data, the CPU implements the functionality of the SpaceVPX System Controller.
The local memory on the DSP board buffers the data transferred between the FMC and the SpaceVPX interface. If the duty cycle of the conversion windows used to sample the echo signal and the sampling frequency are high, then the serial data interface between each DSP module and the CPU module will not support the data rate generated by the four ADCs on the FMC card. In that case, the unused serial data interfaces available on each DSP module can be used to connect the DSP modules to each other, resulting in a mesh topology with a distributed Data Switch.
Figure 6: Synthetic-Aperture Radar with Star Topology Backplane
The Formatter module implements the last processing layer, including image compression and storage. The Mass Memory FMC (MM) securely stores formatted data, which are retrieved and sent to the downlink through the frontal connectors in the CPU board when the satellite is in view of the ground station. The CPU receives commands from and sends telemetry data to the Control and Data Handling (C&DH) subsystem. It worth noting that under the SpaceVPX standard there should be redundancy for compliance. The architecture presented in this section is an unorthodox use of the standard.
If operation in degraded mode is accepted allowing up to one DSP module to fail, then the only single point of failure in the system is the CPU. Adding a second CPU (Formatter) to the system makes it more compliant with the standard and reduces the probability of failure significantly.
If operation in degraded mode is accepted allowing up to one DSP module to fail, then the only single point of failure in the system is the CPU. Adding a second CPU (Formatter) to the system makes it more compliant with the standard and reduces the probability of failure significantly.
Figure 7: Synthetic-Aperture Radar with Star Topology Backplane and Redundant Controller
This system is not fully compliant with the standard either because the DSP modules are not fully redundant. However, though the systems and Backplanes are not compliant, every SpaceVPX and FMC card is fully compliant with the corresponding standard.